SKU/Artículo: AMZ-B0FP2WY5BW
Advanced Assembly Language: Performance Tuning, Reverse Engineering, and Systems-Level Design
Format:
Kindle
Detalles del producto
Disponibilidad:
Fuera de stock
Fuera de stock
Peso con empaque:
0.76 kg
0.76 kg
Devolución:
Sí
Sí
Condición
Nuevo
Nuevo
Producto de:
Amazon
Amazon
Viaja desde
USA
USA
Sobre este producto
- This book is a comprehensive field guide to writing, analyzing, and integrating assembly across modern platforms and instruction sets. It begins by contrasting x86-64, AArch64, and RISC-V architectures and ABIs, grounding readers in register files, condition codes, predication, and instruction encodings. From calling conventions and variadic rules to position-independent code, code models, and the mechanics of GOT/PLT/IAT, it explains how binaries are structured and executed on Linux, Windows, and macOS. Practical attention to assembler ecosystems (GAS, NASM, MASM, yasm, and clang’s integrated assembler) and to unwind metadata and exception interop ensures readers can produce robust, cross-language, cross-OS artifacts with confidence. The heart of the book focuses on performance. It demystifies microarchitecture—out-of-order execution, micro-ops, ports and schedulers, decode and retire bandwidth, branch prediction, caches and TLBs, SMT and NUMA—and shows how these realities shape instruction selection and layout. Readers learn to build sound microbenchmarks, control frequency scaling and thermals, and measure precisely with TSC serialization. A hands-on toolkit—perf, VTune, Linux perf_event, Windows ETW, llvm-mca, uops.info, pmu-tools, flame graphs, and hardware tracing via Intel PT and ARM ETM—supports rigorous profiling, regression detection, and PGO/AutoFDO/LTO pipelines. Optimization chapters translate insights into code: strength reduction, loop unrolling and software pipelining, cache-aware tiling, branchless techniques, register allocation and spill avoidance, prefetching and streaming stores, hot–cold splitting and alignment, constant-time practices, and when to prefer intrinsics over handwritten assembly. Advanced SIMD coverage spans AVX2/AVX-512 and AArch64 NEON/SVE, including masking, shuffles and gathers, reductions, mixed precision, cryptographic instructions, and bit-level tricks with BMI1/BMI2 and PDEP/PEXT. Beyond speed, the book equips you to reason about correctness, safety, and integration. It develops a deep model of concurrency and memory ordering—x86 TSO versus weaker ARM and RISC-V models—along with fences, atomics, lock and lock-free designs, TSX patterns, and efficient waiting primitives. Systems chapters illuminate object formats (ELF, PE/COFF, Mach-O), relocations and symbol visibility, thread-local storage, process startup and syscall paths, unwinding and exceptions, and debug symbol ecosystems. Reverse engineering and dynamic analysis are treated as first-class skills: disassembly strategies, control- and data-flow recovery, compiler idiom recognition, lifting and decompilation (Ghidra, IDA, radare2, BinaryNinja), binary instrumentation (DynamoRIO, Intel Pin, Dyninst, Frida), hotpatching and detours, and anti-instrumentation mitigations. The closing material shows how to design stable ABIs and FFIs, manage stack frames and varargs, build high-throughput I/O paths with zero-copy, io_uring, and IOCP, implement fibers and coroutines, handle signals safely, and harden binaries with CFI, CET shadow stacks, PAC/MTE, RELRO, and CFGuard—culminating in a disciplined build-and-deploy workflow with cross-compilation, linkers, sanitizers, and CFI.
Fuera de stock
Selecciona otra opción o busca otro producto.
Este producto viaja
de USA ![]()
a tus manos en
![]()
a tus manos en
Compra protegida
Disfruta de una experiencia de compra segura y confiable
Tarjetas de Crédito y Débito
Visa
Mastercard
American Express
Pagos a través de PayPal
Compra procesada en dólares con dinero en cuenta o tarjetas internacionales.
Paypal
Pagos a través de MODO
Compra procesada en pesos desde la App de tu banco.
PayPal
Tienes garantía de entrega 