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Artículo: AMZ-B0F3363DCP
Designing Digital Systems With SystemVerilog (v4.0)
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Kindle
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0.84 kg
0.84 kg
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- This was written as an introductory textbook on digital logic design and the SystemVerilog language. The structure of the book makes it useful as both a way to learn digital design, a way to learn SystemVerilog, or a way to learn both. It is targeted at University level courses or at practicing engineers who desire to learn these topics. This book (and its previous versions) have been used for nearly 20 years at Brigham Young University and other places as a textbook for courses on digital systems design. The text chapters are listed below. The chapters are short and concise, typically covering one lecture's worth of material (in the case of courses at Brigham Young University). Roughly 1/3 of the chapters focus on SystemVerilog, each one targeted at teaching how to implement the immediately preceding chapters' digital circuit design concepts using HDL. Additionally, a full chapter on SystemVerilog testbenches for verifying designs is included. The book starts with Boolean Logic and combinational logic design and then moves on to storage elements (flips flops) and sequential circuit design and finite state machine-based design. As can be seen, the SystemVerilog chapters are intermixed through the text but could be covered later than they appear.IntroductionNumber Systems and Binary EncodingsSigned Number Representations, Negation, and ArithmeticBoolean Algebra and Truth TablesLogic GatesBoolean Algebra - Part IIGates - Part IIAn Introduction to Gate-Level Design Using SystemVerilogGate-Level ArithmeticHigher Level Building Blocks: MultiplexersContinuing on With SystemVerilog - Hierarchical Design, Constants, and Multi-Bit SignalsKarnaugh Maps - Optional MaterialGate Delays and Timing in Combinational CircuitsDataflow SystemVerilogLatches and Flip FlopsRegisters and RTL-Based DesignBehavioral SystemVerilog for RegistersBehavioral SystemVerilog for Combinational LogicMemoriesImplementation of Simple Sequential Circuits: IFL, OFL, and TimingState GraphsFinite State MachinesState Machine Design Using SystemVerilogHandling Asynchronous Inputs and Generating Glitch-Free OutputsField Programmable Gate Arrays (FPGAs) - An IntroductionCase Study - Debouncing Switches and Detecting EdgesWriting Testbenches in SystemVerilogCase Study: The Design of a UARTTri-State Drivers and BusesSystemVerilog vs. VerilogAdvanced TimingClock SkewMetastabilityClock Domain CrossingParallelism and Pipelining to Increase Circuit Performance
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